RegViz: Visualize PMU_PERIPH Bitfield

Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /AON /PMU_PERIPH

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Interpret as PMU_PERIPH

ADC2_PGA_EN=Val_0x0, ADC24_EN=Val_0x0, ADC1_PGA_GAIN=Val_0x0, ADC24_PGA_GAIN=Val_0x0, ADC3_PGA_EN=Val_0x0, ADC1_PGA_EN=Val_0x0, ADC3_PGA_GAIN=Val_0x0, ADC2_PGA_GAIN=Val_0x0, ADC24_PGA_EN=Val_0x0

Description

ADC Control Register

Fields

ADC1_PGA_EN	ADC120 PGA enable Note: ADC120 must be put into differential mode when PGA is enabled 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled
ADC1_PGA_GAIN	ADC120 PGA gain value select 0 (Val_0x0): 0 dB 1 (Val_0x1): 6 dB 2 (Val_0x2): 12 dB 3 (Val_0x3): 18 dB 4 (Val_0x4): 24 dB 5 (Val_0x5): 30 dB 6 (Val_0x6): 36 dB 7 (Val_0x7): 42 dB
ADC2_PGA_EN	ADC121 PGA enable Note: ADC121 must be put into differential mode when PGA is enabled 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled
ADC2_PGA_GAIN	ADC121 PGA gain value select 0 (Val_0x0): 0 dB 1 (Val_0x1): 6 dB 2 (Val_0x2): 12 dB 3 (Val_0x3): 18 dB 4 (Val_0x4): 24 dB 5 (Val_0x5): 30 dB 6 (Val_0x6): 36 dB 7 (Val_0x7): 42 dB
ADC3_PGA_EN	ADC122 PGA enable Note: ADC122 must be put into differential mode when PGA is enabled 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled
ADC3_PGA_GAIN	ADC122 PGA gain value select 0 (Val_0x0): 0 dB 1 (Val_0x1): 6 dB 2 (Val_0x2): 12 dB 3 (Val_0x3): 18 dB 4 (Val_0x4): 24 dB 5 (Val_0x5): 30 dB 6 (Val_0x6): 36 dB 7 (Val_0x7): 42 dB
ADC24_EN	ADC24 enable 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled
ADC24_OUTPUT_RATE	ADC24 output rate select
ADC24_PGA_EN	ADC24 PGA enable 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled
ADC24_PGA_GAIN	ADC24 PGA gain value 0 (Val_0x0): 0 dB 1 (Val_0x1): 6 dB 2 (Val_0x2): 12 dB 3 (Val_0x3): 18 dB 4 (Val_0x4): 24 dB 5 (Val_0x5): 30 dB 6 (Val_0x6): 36 dB 7 (Val_0x7): 42 dB
ADC24_BIAS	ADC24 bias control

Links

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